In a synchronous digital system, especially in a computer system, synchronous buses are preferred and commonly used in between subsystems as interface buses (usually chip-to-chip interfaces) to achieve the high bandwidths required for those systems. For synchronous bus transactions to function properly, both sender (multiple bits of binary lines) and receiver sides must operate on a synchronous clock from a common clock oscillator and possibly via phase locked loop circuits on both sides for high frequency systems. Another requirement is that the receiver side must capture all the signal bits of the bus on the same clock cycle to maintain the synchronization.
When the worst-case delay from the sender flip-flops or latches to the receiver flip-flops (FF) (minus the FF setup time) is less than one cycle time (clock period) and the best-case delay is more than the FF hold time, the synchronous bus transaction across the interface has one-cycle delay. That is the simplest synchronous bus interface. However, in high frequency synchronous systems wherein the worst-case delay is more than one cycle and the delay differences among the bits/lines of the bus are more than the cycle time, synchronous bus transactions become much more difficult.
This synchronous bus transaction delay problem has been addressed by others by mainly two approaches. The first approach is to fine tune all the bits of a synchronous bus by adding extra delay (extended wire length) to the bit lines with less delay. This approach tightens the interface physical design requirement and complicates the system design; it is still difficult to determine in which cycle to capture data even with this approach at high frequencies.
The second known approach is using various source-synchronous techniques to align signal bits and the clock (such as “Dynamic Wave-pipelined Interface Apparatus and Methods Therefor.” filed October 1999, IBM U.S. Pat. No. 6,654,897 issued 25 Nov. 2003), as well as signal buffering and rotations at the receiver side (such as “An Elastic Interface Apparatus and Method Therefor.” filed October 1999, IBM U.S. Pat. No. 6,334,163 issued 25 Dec. 2001). Some of those source-synchronous interface and buffering techniques are very sophisticated, but these techniques are also complicated and their implementations require larger circuitry than the method and system of this invention.